1. Field of the Invention
The present invention pertains generally to devices designed to detect incident ionizing radiation in order to form images.
2. Discussion of the Background
In the field of x-ray imaging, imagers based on active matrix imaging arrays are commonly used for numerous medical and non-medical applications. Unless otherwise indicated herein, the term active matrix will be used to refer to the principle of addressing a two-dimensional grid of imaging pixels by way of switches, with an addressing switch in each pixel. Imagers based on active matrix imaging arrays will be referred to as active matrix flat-panel imagers (AMFPIs) or, more concisely, as active matrix imagers. In addition, the terms active matrix array and active matrix imaging array will be used interchangeably.
An AMFPI typically incorporates a single array, including materials that are highly resistant to the effects of ionizing radiation. However, AMFPIs sometimes include two adjacent arrays arranged side-by-side, or four adjacent arrays arranged in a square or rectangle. One reason for the ubiquity and usefulness of active matrix imagers is that the arrays can be manufactured, with acceptable yield and at reasonable cost, at sizes considerably beyond what is possible with conventional crystalline silicon (c-Si) technology. In the case of c-Si technology, pixilated imaging arrays (such as charge coupled devices (CCDs), CMOS sensors, active pixel sensors, and passive pixel sensors) are ultimately limited by the size of the silicon wafers used for fabrication, currently up to ˜300 mm. CCDs, CMOS sensors and active and passive pixel sensors made from crystalline silicon are typically fabricated with dimensions of less than ˜4 cm by 4 cm. While such devices have been made with dimensions as large as ˜20 cm by 20 cm, these devices are hard to yield and costly to produce. Also, while large area devices can be made by tiling small area c-Si arrays, this introduces additional, significant engineering problems, challenges, and costs. In the case of AMFPIs, while active matrix arrays can be made as small as two pixels by two pixels (which would be smaller than 1 cm by 1 cm), active matrix arrays for AMFPIs are typically fabricated in sizes ranging from ˜10 cm by 10 cm up to ˜43 cm×43 cm—greatly exceeding the range of pixilated, c-Si imaging arrays. Moreover, there is no technical reason that prohibits the creation of even larger active matrix imaging arrays—for example, equivalent to the size of the largest active matrix liquid crystal displays (AMLCDs) which have been fabricated as large as ˜108 inches on the diagonal.
In an active matrix imaging array, a two-dimensional grid of imaging pixels is addressed by way of thin-film switches. The array includes a thin substrate on which the imaging pixels are fabricated. Each pixel incorporates a circuit in which an addressing switch is connected to some form of pixel storage capacitor. Each switch usually takes the form of thin-film transistor (TFT), but can also take the form of a thin-film diode or a combination of two or more thin-film diodes. While simple array designs incorporate only a single switch per pixel for purposes of addressing, more complex designs can include additional circuit elements in the pixel that serve to improve the performance and/or extend imager capabilities. Moreover, further circuit elements can be incorporated on the array substrate outside of the pixels. These elements can be configured to carry out such functions as controlling the voltages on the gate address lines, multiplexing signals from the data lines, or for other purposes related to the operation of the array.
Materials used in the fabrication of the arrays include various metals to form features such as address lines, contacts to address lines, traces, vias, electrode surfaces and light blocking surfaces, as well as the source, drain and gate of TFTs. Metals such as aluminum, copper, chromium, molybdenum, tantalum, titanium, tungsten, indium tin oxide and gold, as well as alloys of these materials, such as TiW, MoCr and AlCu, can be used. The thickness of a given metal layer deposited onto the array during fabrication can range from ˜10 nm to several μm. Passivation layers can include materials such as silicon oxynitride (Si2N2O), silicon nitride (Si3N4), polyimide, and Benzocyclobutene polymer (BCB). The thickness of a given passivation layer deposited onto the array surface during fabrication can range from ˜100 nm up to 10 μm. Dielectrics in devices such as TFTs and capacitors can include materials such as silicon nitride (Si3N4), silicon dioxide (SiO2), amorphous silicon, and amorphous silicon nitride (a-Si3N4:H). The thickness of a given dielectric layer deposited onto the array surface during fabrication can range from ˜1 nm to several μm. Typically, multiple metal, passivation and dielectric layers are used to fabricate the various circuit elements in an array.
The semiconductor material for the TFTs (and diode switches) is most commonly hydrogenated amorphous silicon (a-Si), but can also be microcrystalline silicon, polycrystalline silicon (poly-Si), a chalcogenide, or cadmium selenide (CdSe), all of which are suited to large area processing, allowing the manufacture of large area arrays. In this case, the substrates can be made of materials such as glass (such as Corning 7059, 1737F, 1737G, ˜1 mm thick) or quartz (˜1 mm thick) or sheets of stainless steel (˜25 to 500 μm thick). The fabrication of array circuits involves deposition of continuous layers of materials (such as semiconductors, metals, dielectrics and passivations) on the substrate, using area deposition techniques such as plasma enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, and spin coating. In the case of poly-Si, one common method for producing this semiconductor is through crystallization of previously deposited a-Si material by means of an excimer laser. In addition, the features of the circuit (such as those of the TFTs, diodes, photodiodes, capacitors, traces, vias, address lines, and contacts to the address lines) are formed using a combination of photolithographic and etching techniques.
Alternatively, the semiconductor material for these switches can take the form of other materials suitable for large area deposition such as low-temperature a-Si, organic small molecule or polymer semiconductors. Low temperature a-Si is deposited using PECVD, LPCVD and PVD while organic small molecule and polymer semiconductors can be deposited using area deposition techniques or printing techniques. For these semiconductor materials, the substrates can be thin and flexible (made of sheets of material such as polyimide (PI) or polyethylene napthalate (PEM, ˜25 to 200 μm thick). Alternatively, glass, quartz or stainless steel substrates can be used. The features of the arrays circuits can be formed using one, or a combination of photolithographic, etching, subtractive printing and additive printing techniques. Yet other semiconductor materials that can be used, both for TFTs and other devices, include carbon nanotubes and graphene. Yet other semiconductor materials that can be used, both for TFTs and other devices, include oxide semiconductors including, but not limited to ZnO, InGaZnO, InZnO, ZnSnO (and any other oxides containing Zn), SnO2, TiO2, Ga2O3, InGaO, In2O3, and InSnO. These oxide semiconductors are known to exist in amorphous or polycrystalline forms, and as available are suitable for the invention. For all types of semiconductors, the materials are used in their intrinsic form, as well as in doped forms to provide p-doped or n-doped semiconductor material.
TFTs have a gate, a source and a drain. The magnitude of the current flowing through the semiconductor channel of the TFT, between the source and the drain, is controlled by a variety of factors such as the width and length of the TFT channel, the mobility of the semiconductor used in the channel, the magnitude and polarity of the voltage applied between the gate and the source, and the voltage difference between the source and drain. Manipulation of the voltage applied to the gate allows the transistor to be made highly conducting (described as being “on”) or highly non-conducting (described as being “off”).
FIGS. 1 to 4 show examples of a-Si and poly-Si TFTs. FIG. 1 is a schematic drawing illustrating the structure of one form of an a-Si TFT. FIG. 2 is a schematic, cross sectional view, corresponding to the position of the plane indicated by the wire frame in FIG. 1. The symmetry of the structure of this a-Si TFT is such that this cross sectional view would remain largely unchanged for any position of the wire frame along the width of transistor. FIG. 3 is a schematic drawing illustrating the structure of one form of a poly-Si TFT. The version shown has a single gate but two or more gates are also possible. FIG. 4 is a schematic, cross sectional view corresponding to the position of the plane indicated by the wire frame in FIG. 3. Compared to the a-Si TFT illustrated in FIGS. 1 and 2, the poly-Si TFT illustrated in FIGS. 3 and 4 has a lower degree of symmetry by virtue of the presence of the vias, so that a cross sectional view of the transistor would vary considerably for other positions of the wire frame along the width of the transistor.
An active matrix imager typically includes: (a) an active matrix imaging array; (b) a layer of material overlying the array which serves as an x-ray converter; (c) external electronics connected to the array by way of contact pads located at the ends of the data and gate address lines. Some of these electronics are located in close proximity to the perimeter of the array and provide digital logic that serves to assist in the control of the voltages and timings necessary to operate the array, as well as to amplify, multiplex, and digitize the analog signals extracted from the pixels along the data address lines. These electronics also include voltage supplies required to operate the array and the peripheral electronics, as well as a digital electronic interface to allow communication between the electronics and one or more computers; (d) one or more computers to send control information to the electronics, to receive digital pixel information from the electronics, to synchronize the operation of the array with the delivery of radiation from the x-ray source, and to process, display and store this imaging information; and (e) the software, firmware and other coded instructions used in the computers and in the digital logic of the electronics.
The array substrate, thin-film electronics and x-ray converter are all relatively thin, with a combined thickness of less than 1 cm. This allows these elements, along with peripheral electronics, to be configured into a package having a thickness as compact as ˜1 cm, similar to that of a standard x-ray film cassette or computed radiography (CR) cassette. Electronic x-ray imagers with such profiles, irrespective of the technology upon which the imagers are based, are often called flat-panel imagers (FPIs). In order to distinguish from flat-panel imagers created from other technologies (such as tiled CMOS sensors), a descriptive term that pertains broadly to imagers based on thin-film electronics is thin-film flat panel imagers. In the specific case of imagers employing active matrix arrays, the term active matrix flat-panel imagers (AMFPIs) is appropriate.
The pixels for an active matrix imaging array are arranged in rows and columns. For an array using TFT switches, and for a given row of pixels, the gates of all of the addressing TFTs along that row are connected to a common gate address line, with one gate line per pixel row. External manipulation of the voltage applied to each gate address line therefore allows control of the conductivity of all the addressing TFTs along that row. For a given column of pixels, the drains of all of the addressing TFTs along that column are connected to a common data address line, with one data address line per pixel column.
During operation of an AMFPI, all the addressing TFTs are kept non-conducting during delivery of the x-rays in order to allow collection of imaging signals in the pixel storage capacitors. The imaging signals stored in these capacitors are read out, typically one row of pixels at a time, by making the addressing TFTs in that row conducting. This allows the imaging signals to be sampled from the corresponding data address lines at the full spatial resolution of the array. For a given data address line, each sampled signal is amplified by a preamplifier and digitized by an analog-to-digital converter, both located external to the array. Of course, the imaging signals can be sampled from two or more consecutive rows at a time, which decreases the read-out time, but at the cost of reduced spatial resolution.
Active matrix imagers are most commonly operated in conjunction with an x-ray source, although they can be operated with sources of other forms of ionizing radiation such as gamma rays, electrons, protons, neutrons, alpha particles, and heavy ions. The pixel pitch (which is equal to the width of one pixel) and size of the array, the frame rate capabilities of the array and imager, and the beam energy, filtration and temporal characteristics of the x-ray source are all chosen to match the needs of the imaging application. Diagnostic and interventional medical imaging can be performed with arrays having pixel pitches of ˜25 μm up to ˜200 μm and with ˜15 to 40 kVp x-ray beams for many forms of breast imaging applications (including mammography, breast tomosynthesis, breast computed tomography, and image-guided biopsies). Diagnostic and interventional medical imaging can also be performed with arrays having pixel pitches of ˜75 μm up to ˜1000 μm and with ˜50 to 150 kVp x-ray beams for many forms of radiographic, fluoroscopic, and tomographic applications (including chest imaging, chest tomosynthesis, dual-energy imaging, angiographic procedures, interventional procedures, biopsy procedures, imaging of extremities, pediatric imaging, cardiac imaging, cone beam computed tomography of abdomen, chest, head, neck, teeth, as well as for simulation, localization, verification and quality assurance in radiation therapy). In addition, medical imaging can be performed with pixel pitches of ˜300 μm up to ˜1000 μm with the treatment beams used for external beam radiation therapy. In this case, the radiation source can be a Co-60 source (with an average energy of ˜1.25 MeV), or the output from a linear accelerator or any other type of accelerator that produces megavoltage radiation ranging from ˜3 up to 50 MV. Medical imaging using active matrix imagers can also be performed with a brachytherapy source, such as cesium-137 (137Cs), iodine-125 (125I), iridium-192 (192Ir), palladium-103 (103Pd), strontium-90 (90Sr) and yttrium-90 (90Y). In addition, non-medical applications (such as industrial radiography) use active matrix imagers in conjunction with all of the radiation sources described above, as well as with sources providing x-ray energies ranging from a few kVp up to ˜15 kVp. The design and capabilities of the x-ray converters and of the associated electronics for flat panel imagers are matched to the design of the arrays, the manner of operation, and the needs of the various non-medical applications.
Imagers based on active matrix arrays may be generally divided into two categories, based upon the manner in which x-rays are detected by the converter, referred to as indirect detection and direct detection. For indirect detection imagers, some of the energy of incident x-rays that interact with the converter is first converted into optical photons and a fraction of these photons are subsequently converted into electrical signal that is stored in the pixel storage capacitors of the array. For direct detection imagers, some of the energy of the incident x-rays that interact with the converter is directly converted into electrical signal that is stored in the pixel storage capacitors.
For indirect detection imagers, the converter takes the form of a scintillator. For many applications, cesium iodide doped with thallium (written as CsI:Tl or CsI:Te), typically grown so as to form a structure with aligned, needle-like crystals) or gadolinium oxysulfide doped with terbium (written as Gd2O2S:Tb or Gd2O2S:Tb3+, also called GOS, typically in the form of a powder phosphor screen) is used. However, other scintillators are also possible such as cesium iodide doped with sodium (written as CsI:Na or CsI:Na+), sodium iodide doped with thallium (written as NaI:TI or NaI:Tl+), calcium tungstate (CaWO4), zinc tungstate (ZnWO4), cadmium tungstate (CdWO4), bismuth germanate (Bi4Ge3O12, also called BGO), lutetium yttrium orthosilicate doped with cerium (written as Lu1.8Yb0.2SiO5:Ce or Lu1.8Yb0.2SiO5:Ce3+, also known as LYSO), and gadolinium silicate doped with cerium (written as Gd2SiO5:Ce or Gd2SiO5:Ce3+, also known as GSO). Yet other scintillators are possible such as BaFCl:Eu2+, BaSO4:Eu2+, BaFBr:Eu2+, LaOBr:Tb3+, LaOBr:Tm3+, La2O2S:Tb+, Y2O2S:Tb3+, YTaO4, YTaO4:Nb, ZnS:Ag, (Zn,Cd)S:Ag, ZnSiO4:Mn2+, CsI, LiI:Eu2+, PbWO4, Bi4Si3O12, Lu2SiO5:Ce3+, YAlO3:Ce3+, CsF, CaF2:Eu2+, BaF2, CeF3, Y1.34Gd0.6O3:Eu3+, Pr, Gd2O2S:Pr3+, Ce, SCGl, HFG:Ce3+ (5%) and C14H10. For many types of scintillator material (such as CsI:Tl, BGO and LYSO), the converter can take the form of a segmented detector in which small individual elements of scintillator material, each with a cross sectional area approximately equal to, or smaller than the pixel pitch of the imaging array (or a multiple of the pixel pitch of the array), are assembled with septal wall material separating the elements to form an area detector that provides optical isolation between elements, thereby preserving spatial resolution.
A layer of material, referred to as encapsulation or as an encapsulation layer, may be deposited to form a top layer of the scintillor in order to mechanically and chemically protect the scintillator.
For indirect detection AMFPIs, the pixel storage capacitor takes the form of an optical sensor, such as a photodiode or a metal insulated semiconductor (MIS) structure. Such optical sensors commonly incorporate a-Si semiconductor—a material that is well suited for imaging of ionizing radiation by virtue of the fact that the signal, noise and dark current properties of a-Si sensors are only very weakly affected by even extremely high doses of radiation. The properties of TFTs based on a-Si and poly-Si are also only weakly affected by extremely high doses of radiation, making such TFTs well suited for imaging of ionizing radiation.
One form for the structure of an a-Si photodiode includes a bottom electrode (which is connected to the source of the addressing TFT), a doped layer (n+ doped a-Si, ˜10 to 500 nm thick and preferably ˜50 to 100 nm thick), a layer of intrinsic a-Si (preferably ˜0.5 to 2.0 μm thick), a second doped layer (p+ doped a-Si, ˜10 to 500 nm thick and preferably ˜5 to 20 nm thick), and a top electrode which is made of a material transparent to visible light (such as indium tin oxide, ITO). In one alternative form of such an a-Si photodiode structure, the dopings of the upper and lower a-Si layers are interchanged. Minimizing the thickness of the top doped a-Si layer reduces the fraction of optical photons that are absorbed in this layer, helping to maximize the imaging signal recorded in the pixel.
An example of a pixel circuit for an indirect detection, active matrix imaging array is schematically illustrated in FIG. 5. The circuit elements depicted in this figure include the photodiode (PD) and the pixel addressing transistor (TFT). The source, drain and gate of the TFT, surrounded by a dashed ellipse, are labelled. A second dashed ellipse emphasizes that the photodiode, which is the optical sensor for the pixel, also serves as the pixel storage capacitor, with a capacitance of CPD. The gate address line and data address line corresponding to the row and column, respectively, of the depicted pixel are also shown. The magnitude of the reverse bias voltage applied to the top electrode of the photodiode is VBIAS. This voltage is provided by an external voltage supply. VBIAS is typically set to a value in the range of ˜1 V to 8 V.
FIG. 6 is a schematic, cross-sectional illustration of one structural implementation, referred to as the baseline architecture, of a pixel design corresponding to the pixel circuit in FIG. 5. In this implementation, the addressing TFT shares the surface area of the pixel with a number of other elements including a discrete a-Si photodiode having a stacked structure, address lines, and the gaps between the address lines, photodiode and TFT.
In FIG. 6, the general location of the a-Si addressing transistor (TFT), with only the drain, source and gate illustrated, is indicated by a dashed ellipse. The bottom electrode of the photodiode is formed by an extension of the metal used to form the source of the TFT. The remaining layers of the photodiode, which do not overlap with the TFT, are patterned so as to be aligned with the edges of the bottom electrode and in this way form a stacked structure. These layers include a layer of n+ doped a-Si, a layer of intrinsic a-Si, a layer of p+ doped a-Si, and a layer of ITO serving as an optically transparent top electrode. A reverse bias voltage, of magnitude VBIAS, is applied to the top electrode of the photodiode by way of a bias line, creating an electric field, {right arrow over (E)}, across the photodiode. The direction of the data address line, which is connected to the drain of the TFT by way of a metal via, and of the bias line, is orthogonal to the plane of the drawing. The approximate location of passivation material is schematically indicated by shading. This includes passivation material that is deposited over the entire top surface of the array in order to encapsulate the array, protecting the array mechanically and preventing unintended electrical contact with the bias and data address lines. An x-ray converter in the form of a scintillator, which extends over the entire array, is also depicted. Incident x-rays (wavy arrows) generate optical photons (straight, faint arrows) in the scintillator. Some of the optical photons enter the intrinsic layer of the photodiode creating electrons and holes which drift toward the electrodes by virtue of the electric field, thereby creating imaging signal that is stored in, and eventually read out from, the pixel.
For direct detection, active matrix, flat-panel imagers, the converter can take the form of a layer of photoconductive material, with a thickness sufficient to stop a large fraction of the incident x-rays. One suitable photoconductive material is amorphous selenium, a-Se, which can be fabricated up to ˜2000 μm thick, and is preferably fabricated with thicknesses ranging from ˜200 to 1000 μm. Other photoconductive materials that are suitable as direct detection converters include single crystal and polycrystalline forms of lead iodide (PbI2), mercuric iodide (HgI2), lead oxide (PbO), cadmium zinc telluride (CdZnTe), cadmium telluride (CdTe), Bi2S3, Bi2Se3, BiI3, BiBr3, CdS, CdSe, HgS, Cd2P3, InAs, InP, In2S3, In2Se3, Ag2S, PbI4−2 and Pb2I7−3. The choice of thickness for the photoconductor increases with increasing x-ray energy, so as to achieve conversion of a reasonably large fraction of the x-rays, which can be anywhere from ˜10% to 90% at diagnostic energies and from ˜1% to 10% at radiotherapy energies.
In the case of imaging using megavoltage radiation, for example for external beam radiation therapy imaging or for industrial radiography, including scanning for security applications, a thin (˜1 mm) metal plate is typically positioned over the converter (directly on the scintillator, for indirect detection, or directly on the encapsulation over the top electrode covering the photoconductor for direct detection). The composition of this plate can take many forms including copper, steel, tungsten and lead. An example of a pixel circuit for a direct detection, active matrix imaging array is schematically illustrated in FIG. 7. The circuit elements depicted in this figure include the photoconductor (PC), the pixel addressing transistor (TFT), and (as indicated by a dashed ellipse) a pixel storage capacitor with capacitance CSTORAGE. The source, drain and gate of the TFT, surrounded by another dashed ellipse, are labelled. A third dashed ellipse emphasizes that the photoconductor has capacitance CPC and also acts like a large resistor, of resistance RPC, in the circuit. The gate address line and data address line corresponding to the row and column of the depicted pixel are also shown. The magnitude of the bias voltage applied to the top electrode of the photoconductor is VBIAS. This voltage is provided by an external voltage supply. The value of VBIAS used depends upon the type of photoconductor material and generally increases in proportion to the layer thickness of that material. For a-Se, VBIAS is typically ˜10 V per micron of thickness. Thus, for a 1000 μm layer of a-Se, VBIAS will be ˜10,000 V. For HgI2, VBIAS is typically in the range of ˜0.5 to 2.0 V per micron. Thus, for a 500 μm layer of HgI2, VBIAS will be ˜250 to 1,000 V. The photoconductive layer can also be operated in avalanche mode, with the value of VBIAS across that layer typically higher—in the range of ˜50 V to 100 V per micron for the example of a-Se. In this case, the avalanche layer may be made sufficiently thick to stop a large fraction of x-rays itself, or it may be made thin, with a layer of photoconductor or scintillator (such as a-Se or CsI:Tl, respectively, of sufficient thickness to stop a large fraction of the incident x-rays) deposited over it. In this case, the purpose of the avalanche layer is to amplify the signal from the overlying converter.
FIG. 8 is a schematic, cross sectional illustration of one structural implementation of a pixel design corresponding to the pixel circuit in FIG. 7. In this implementation, the addressing TFT shares the surface area of the pixel with the pixel storage capacitor, with the address lines, and with gaps between the address lines, storage capacitor and TFT. The photoconductor structure (including a bottom electrode, a layer of photoconductive material, and a top electrode) resides above the plane (i.e., above the level) of the addressing TFT.
In FIG. 8, the general location of the a-Si addressing transistor (TFT), with only the drain, source and gate illustrated, is indicated by a dashed ellipse. For the pixel storage capacitor, the location of which is indicated by a second dashed ellipse, only the top and bottom electrodes are illustrated. The top electrode of the pixel storage capacitor is formed by a back contact, which is an extension of the metal used to form the source of the TFT. The bottom electrode for the photoconductor is connected to the TFT by way of a via (indicated by a third ellipse) to the back contact, and does not extend over the TFT. A thick, continuous layer of photoconductor material (which acts as an x-ray converter) is deposited across the entire array, putting that material in contact with the bottom electrode. A continuous top electrode is deposited over the entire photoconductor surface. A bias voltage, of magnitude VBIAS, is applied to the top electrode so as to establish an electric field across the photoconductor. A layer of material, referred to as encapsulation or as an encapsulation layer, is deposited over the entire top electrode in order to encapsulate the array, protecting the array mechanically and chemically, and preventing unintended electrical contact with the top electrode. The direction of the data address line, which is connected to the drain of the TFT by way of a metal via, is orthogonal to the plane of the drawing. The location of passivation material is approximately indicated by shading. Note that in alternate configurations of direct detection pixels and arrays, a thin layer of material (typically ˜1 to 10 microns thick, acting as a barrier, dielectric or doped layer) may be deposited between the bottom electrode and the photoconductor, or between the top electrode and the photoconductor. Alternatively, such a thin layer of material may be deposited in both locations, and may be different in type and thickness in each location.
For indirect detection active matrix imaging arrays having the baseline architecture illustrated in FIG. 6, the addressing TFT and the photodiode are in direct competition with each other, and with other pixel elements, for area in the pixel. This is apparent in FIG. 6 as well as in a corresponding schematic rendering of four pixels appearing in FIG. 9. It is further apparent in FIG. 10 in which photomicrographs of pixels obtained from a pair of indirect detection active matrix arrays are shown. Generally, indirect detection active matrix arrays are designed so as to make the area of the photodiode as large as possible. In addition, for array designs in which the bias line extends over the top surface of the photodiode, the area of these lines and of associated vias (both of which are optically opaque and block light from reaching the photodiode) are made as small as possible. For a given array design, the fraction of the pixel area that is occupied by photodiode surface that is open to incident light from above is referred to as the optical fill factor.
Maximization of optical fill factor is motivated by the fact that more efficient use of the incident light from the overlying scintillator increases pixel signal size, and thus the signal-to-noise ratio of the imager, leading to improved image quality. Maximizing optical fill factor is particularly important for array designs that serve applications requiring small pixel pitches (for example, under ˜100 μm), or applications in which the imager is operated at low exposures (such as the low exposure region of fluoroscopy, where the exposure per frame is less than ˜1 μR).
A high optical fill factor encourages minimization of the size of the addressing TFT, the widths of the address lines, the width of the bias line, and the gaps between the photodiode, the TFT and the address lines. However, the fabrication process imposes a minimum feature size on every element of the design. Furthermore, the address and bias lines must be sufficiently wide to limit the electrical resistance along these lines (since high resistance would negatively affect the temporal and/or electrical operation of the array, as well as possibly decrease signal-to-noise performance). In addition, the gaps must not be so narrow as to lead to unintended contact (and thus electrical shorting) between pixel elements or to high levels of parasitic capacitance (which can degrade the signal-to-noise ratio and the temporal performance). Finally, the ratio of the width to length of the TFT channel (called the aspect ratio) must be sufficiently large so as to provide the magnitude of TFT-on current required for the desired array readout speed (since TFTs with higher aspect ratios provide higher levels of current in their conducting mode). FIG. 10 illustrates a practical example of these considerations in which the optical fill factor of an early array design, shown in FIG. 10(a), has been significantly increased in a later design, shown in FIG. 10(b), through decreases in the sizes of gaps, address lines and the TFT, assisted by a decrease in the minimum feature size. The challenge of maintaining a large optical fill factor becomes more difficult as pixel pitch decreases, since the area occupied by the address lines, gaps, and addressing TFT consumes an ever-greater fraction of the pixel area.
A highly effective method to circumvent the aforementioned restrictions on optical fill factor is to implement pixel architectures in which the photodiode structure is positioned above the plane (i.e., above the level) of the addressing TFT. A variety of such out-of-plane architectures are possible, and two such architectures are shown in FIGS. 11 and 12. In these illustrations, the out-of-plane photodiode structure overlaps a portion, or all, of the addressing TFT, in order to maximize optical fill factor.
The photodiode in FIG. 11 includes a discrete, stacked structure aligned with the bottom electrode. As in FIG. 6, a single addressing TFT is connected to a discrete a-Si photodiode with three a-Si layers and with top and bottom electrodes. However, in this pixel architecture, the bottom electrode of the photodiode is located above the plane of the addressing TFT. The bottom electrode is connected to the TFT by way of a via (the location of which is indicated by a dashed ellipse) to the back contact, which is an extension of the metal used to form the source of the TFT. The a-Si layers and the top electrode of the photodiode are patterned to form a stack aligned with the bottom electrode. The direction of both the data address line (the location of which is indicated by the solid ellipse), and the bias line is orthogonal to the plane of the drawing.
The photodiode in FIG. 12 has a structure in which some of the layers are continuous. As in FIG. 11, a single addressing TFT is connected to an a-Si photodiode located above the plane of the TFT. However, in this pixel architecture, the p+ doped and intrinsic layers are not patterned, but rather are continuous across the array to assist in maximizing the optical fill factor. The doped a-Si layer is patterned to align with the bottom electrode of the photodiode to inhibit charge sharing between neighboring pixels. The bottom electrode is connected to the TFT by way of a via (the location of which is indicated by a dashed ellipse) to the back contact, which is an extension of the metal used to form the source of the TFT. The direction of the data address line (the location of which is indicated by the solid ellipse) is orthogonal to the plane of the drawing.
FIGS. 13 and 14 correspond to an actual realization of an indirect detection active matrix array design having the pixel architecture portrayed in FIG. 12. FIG. 13 is a schematic rendering of four pixels while FIG. 14 is a photomicrograph of a pixel from an array.